SystemVerilog
Hardware description / Verilog · 2002Actively developedHardware design and verification with RTL, assertions and object-oriented testbench facilities.
Concurrent · Hardware description
Links
- Reference / standard
- https://verilator.org/guide/latest/
- Wikipedia (English)
- https://en.wikipedia.org/wiki/SystemVerilog
Tracked release
- Version
- IEEE 1800-2023
- Artifact
- Language standard
- Published
- 2024-02-28
- Source checked
- 2026-10-22
Use & ecosystem
- Suited for
- Hardware design / verification
- Family / tradition
- C-style, Hardware description
- Maturity
- Established
- Ecosystem breadth
- Focused
Sustained industrial design and verification use supports Established. The ecosystem is deep but concentrated in electronic design and verification.
Industry & practical use
ASIC and FPGA design, simulation, assertions and verification environments are central uses. A verification class hierarchy is not necessarily synthesizable hardware.
Compilers, libraries & tooling
Commercial simulators, synthesis tools and open-source tools such as Verilator support different subsets. UVM belongs to verification methodology and libraries, not the entire synthesizable language.
Platforms & deployment
- General toolchains
- FPGA, ASIC
- Specialized tooling
- None catalogued
- Native cross-compilation
- Not the usual deployment model
Hardware targets are FPGA and ASIC flows. The host OS of a simulator is described by that tool, not treated as a software deployment target for the design.
Synthesis and hardware elaboration are separate from compiling an ordinary native application for another OS or CPU.
Project health & support
IEEE, Accellera and EDA vendors provide established standards and tooling processes. Tool compatibility and supported revision details remain important purchasing and deployment constraints.
Use, ecosystem & platform assessment reviewed 2026-10-22 · Sources below
History & origin
Accellera developed SystemVerilog extensions in the early 2000s, building on Verilog and donated language technologies. IEEE standardization subsequently unified the design and verification language.
- Creators
- Accellera, Contributing EDA companies
- Origin
- 2002 — First Accellera SystemVerilog release.
Influences & descendants
Influenced by
Influenced in this catalogue
- No linked entries yet.
Language features
- Typing
- Static
- Execution
- Simulation, Synthesis
- Block structure
- Explicit delimiters
- Semicolons
- Required
- Lexical closures
- No
- Namespaced modules
- Yes
- Pattern matching
- Partial
- Macro system
- Textual preprocessor macros
Implementation notes
- Preprocessor macros replace tokens and do not qualify as syntactic AST macros. Tagged-union matching is specialized and tool support varies.
Sources & references
- Project overview
- https://standards.ieee.org/ieee/1800/7743/
- Language / implementation reference
- https://verilator.org/guide/latest/
- Accellera standards access
- https://www.accellera.org/downloads/ieee
Use, ecosystem & platform sources
- Project overview
- https://standards.ieee.org/ieee/1800/7743/
- Language / implementation reference
- https://verilator.org/guide/latest/
- Accellera standards access
- https://www.accellera.org/downloads/ieee
See the classification definitions for implementation-dependent features. Influence links cover the entries documented here.